(1) Field of the Invention
The present invention relates to a semiconductor wafer on which a film with low dielectric constant is formed, semiconductor device with wires or the like in the above film with low dielectric constant, and methods of producing the same wafer and device.
(2) Description of the Prior Art
Recently, techniques for utilizing materials of low dielectric constant, which can decrease inter-wire capacity, have been extensively developed to cope with higher-speed operation of devices.
A process for forming a damascene copper wiring system of low dielectric constant material is described by referring to FIGS. 6 and 7.
Referring to FIG. 6(a), the silicon nitride film 1 is formed on the lower wiring layer on the silicon substrate (both not shown), and then is coated with the Methyl Silsesquioxane (MSQ) film 2. The MSQ film 2 is formed by, e.g., spin coating. It is then coated with the silicon oxide film 4 of silicon oxide, which works, e.g., to improve resistance to oxygen plasma ashing while the resist used in the subsequent step is separated, and to prevent dielectric constant from increasing in the presence of moisture. The wiring grooves are formed by dry etching in the MSQ film 2 and the silicon oxide film 4 to reach the silicon nitride film 1, after the silicon oxide film 4 is covered with the resist mask (not shown) (FIG. 6(c)).
Next, the entire surface is coated with the barrier metal film 5 by an adequate method, e.g., sputtering (FIG. 7(a)), and then with the copper film 6. The surface is then planarized by CMP, while leaving the copper film 6 in the wiring grooves, to complete the damascene wiring system (FIG. 7(b)).
In the semiconductor device prepared by the above procedure, since the space between the wires is filled with the MSQ film 2 with low dielectric constant, crosstalk can effectively be prevented. In this device, however, the silicon oxide film 4 tends to peel off from the organic MSQ film 2 on which it is formed in the subsequent step as shown in FIG. 5, because of insufficient adhesion between them at the interface, since the former is of an inorganic material while the latter of an organic material. The MSQ film 2 will have dielectric constant decreasing as its organic component content increases. On the other hand, the silicon oxide film 4 is preferably inorganic to have better characteristics, e.g., higher resistance to ashing. Therefore, they tend to be less compatible with each other, leading to peering at the interface. The peering causes lowered yield in the wiring step.
An attempt has been made to prevent the peering by replacing the MSQ film 2 with a film containing no organic compound, such as that of Hydrogen Silisesquioxane (HSQ). However, the HSQ film has a higher dielectric constant than the MSQ film.
The other measures to prevent the peering are to treat the MSQ film with ozone, UV-ozone or oxygen plasma, thereby improving its adhesion to the inorganic film. These methods, however, involve problems, e.g., penetration of water into the film, increased dielectric constant of the insulation film, and roughened film surface to leave residue. Therefore, the measures free of the above problems to improve adhesion have been demanded.
On the other hand, the planarizing process is becoming increasingly important for the interlayer insulation, while the fine machining techniques are required to meet the higher standards. Insufficient flatness will cause various problems, e.g., blurred exposure focus, difficulty in processing photoresist, and increased quantity of residual etchant during the etching process subsequent to masking with the photoresist. In order to make the interlayer insulation film flatter, a material with good reflow characteristics, e.g., BPSG (boron phosphate glass), has been used for the insulation film formed prior to the metal wiring process. The conventional process for forming a memory device or the like incorporating BPSG is described by referring to FIGS. 8 and 9.
Referring to FIG. 8(a), the gate electrode 60 which also serves as the word line is formed on the silicon semiconductor substrate. The processes through which such status is achieved will be described. First, the field insulation film 53 is formed by selective oxidation on the surface of the semiconductor substrate 51 composed of p-type single-crystal silicon. Then, the phosphorus ion is implanted to form the p-type well region 52. Then, the silicon oxide film 61 is formed by thermal oxidation, and coated with the polycrystalline silicon film 62, tungsten silicide (WSi) film 63 and silicon nitride film 64. These films are patterned by etching to form the gate electrode 60. Then, the silicon nitride film is formed and treated by anisotropic etching, to form the side-wall insulation film 65 of silicon nitride on the side of the gate electrode 60. Then, ion is implanted to form the impurity diffusion layer 54. These processes complete the assembly shown in FIG. 8(a).
Then, the BPSG film 55 is formed by CVD method. It is annealed with nitrogen to reflow, and etched back with buffered hydrogen fluoride (BHF), to planarize the BPSG film 55 surface (FIG. 8(b)).
The BPSG film 55 surface is covered with a patterned photoresist (not shown), and then subjected to dry etching with the photoresist serving as the mask, to form the contact hole 57 (FIG. 9(a)), during which the side-wall insulation film 65 works as the etching-stopping film for self-alignment of the contact hole 57. Then, the film is treated with buffered hydrofluoric acid to remove the natural oxide film on the impurity diffusion layer 54.
Then, the polycrystalline silicon film 72 is formed in such a way to fill the contact hole 57, and doped with phosphorus. The BPSG film is further coated with the tungsten silicide (WSi) film 73 and silicon oxide film 74, and etched to form the bit line (FIG. 9(b)).
Recently, the gap between the gate electrodes (word lines) has become very narrow at 0.2 μm or less, to satisfy the requirements for more integration, and the interlayer insulation film material is required to have better gap-filling characteristics. The required gap-filling characteristics become severer for highly integrating processes, such as those described above, which invariably need the so-called self-alignment techniques to secure insulation between the contact hole and wiring layer by the side-wall insulation film of the gate electrode. It is difficult for the conventional processes which use BPSG as the insulation film material to meet these requirements, and use of a material of better gap-filling characteristics is essential. The inorganic SOG films such as HSQ film and organic SOG films such as MSQ film are considered as the ones which can meet the above requirements. However, HSQ is low in resistance to chemical solutions, and difficult to form the contact hole of the shape as designed, because of side etching proceeding during the process of removing the natural oxide film with buffered hydrofluoric acid. The inorganic SOG films other than that of HSQ generally have a disadvantage of being easily cracked. As a result, the organic SOG films, e.g., MSQ film, have been most suitably used. The organic film with low dielectric constant, e.g., MSQ film, has good characteristics of filling a narrow gap, and can secure high flatness.
When an organic material of low dielectric constant, e.g., MSQ, is used, it is necessarily coated with an inorganic protective film, e.g., silicon oxide film, to have improved characteristics, e.g., resistance to ashing. This will cause the problem of peering of the inorganic protective film from the MSQ film, as described earlier.